Chandinee Moyya
Design Verification Engineer @Synopsys
- Role
- Design Verification Engineer at Synopsys Inc
- Location
- Srikakulam, IN
- LinkedIn followers
- 500 followers
About Chandinee Moyya
As a B. Tech ECE student, I am driven by a keen interest in VLSI Design Verification. Proficient in Digital electronics,Verilog, System verilog,UVM,RAL methodologies. I have hands-on experience with FPGA projects. Aspiring to contribute my skills and passion to the industry, I am eager to explore opportunities that align with my goal of becoming a skilled and innovative Design Verification Engineer.
Experience
Design Verification Engineer
Jun 2024 — Present · Hyderabad, IN
Education
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM
Pre-University Course
2018 — 2020
Andhra Pradesh Model School (APMS) Edulavalasa Polaki Srikakulam
Secondary Education
2013 — 2018
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM
B. Tech
2020 — 2024
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