Upender Pasunooti
Design Verification Engineer at Adani Defence and Aerospace |Ex-DRDO Research Fellow |MTech- JNTUH |GATE EC 2018- AIR 628 |VLSI|Semiconductors
- Role
- Design Verification Engineer at Micron Technology
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Upender Pasunooti
About 1.Design verification engineer with overall 8 years of experience…
Experience
Design Verification Engineer
Aug 2022 — Present · Hyderabad, IN
Project 1: PCIe Gen5 Transaction Layer IP Verification•Implement a comprehensive verification test bench for the PCIe Gen5 Transaction Layer.•Verify correct Transaction Layer Packets (TLPs) handling for data, completion, and acknowledgment.•Validate the flow control mechanisms, including credit-based flow control for efficient data transfer.•Confirm compliance with PCIe Gen5 protocol specifications.•Worked on test cases related to memory and configuration transactions.• I worked on bringing up the Flow Control initialization Test and added constraints in the sequences.•Worked on bringing up a test case related to the completion Timeout scenarios.Project 2: DDR4 IP Verification Project.•Developed and implemented UVM-based test benches for verifying DDR4 memory controller and PHY interfaces, ensuring compliance with JEDEC DDR4 specifications.•Designed and executed directed and constrained-random test cases, achieving high functional and code coverage using System Verilog and UVM.•Verified read/write transactions, burst operations, bank interleaving, refresh cycles, and timing constraints, and debugging using waveform analysis tools.•Developed scoreboards, monitors, and functional checkers to validate data integrity, command sequencing, and protocol adherence.•Evaluated latency, bandwidth, and power efficiency, optimizing test scenarios to validate DDR4 controller performance.Project 3: AMBA Protocols AXI, AHB and APB•Performed comprehensive functional verification of AMBA protocols, including AXI4, AHB, and APB, ensuring compliance with the AMBA specifications. •Designed and implemented System Verilog UVM-based test benches to verify AMBA interfaces, covering address decoding, burst operations, write interleaving, and read/write data integrity.• Developed, directed, and constrained-random test cases for complex scenarios, including multiple outstanding transactions, arbitration, and split transfers.
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