Undadi Shailaja.
Lead Design Verification Engineer @HCLTech
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WORK HISTORY
Lead Design Verification Engineer @HCLTech
IN
EDUCATION
Princeton Institute of Engineering & Technology For Women
Diploma , Electronics and communication
CMR Institute of Technology, Hyderabad
B. Tech, Electrical and Electronics Engineering
Gokaraju Rangaraju Institute of Engineering and Technology
M. Tech vlsi , Vlsi design
ABOUT UNDADI SHAILAJA.
I am a highly motivated and detail-oriented Verification Engineer with expertise in UVM, SystemVerilog, and functional verification methodologies. I specialize in building scalable and reusable testbenches, ensuring thorough coverage, and debugging complex designs. Key Skills & Expertise: UVM-based Testbench Development – Creating modular and reusable test environments SystemVerilog Assertions & Functional Coverage – Ensuring design correctness and completeness Verification Planning & Execution – Crafting verification strategies, test plans, and coverage-driven verification Debugging & Root Cause Analysis – Using industry-standard simulators to identify and resolve issues efficiently Scripting & Automation – Writing scripts in Perl and Python to automate verification processes Protocol Expertise – Experience with protocols like AXI, I2C, SPI, UART, PCIe Passion for Innovation & Problem-SolvingI am passionate about solving complex verification challenges and continuously improving verification methodologies. My ability to work in fast-paced environments, collaborate with cross-functional teams, and optimize test strategies makes me an asset to any team. Open to Learning & NetworkingI believe in continuous learning and staying updated with the latest trends in design and verification. I am always open to discussing UVM methodologies, debugging strategies, and industry innovations.
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