Umer I. Cheema
Deep Learning Hardware Architect @ Intel | PhD | Senior Member IEEE
- Role
- Deep Learning Hardware Engineer at Intel
- Location
- Portland, OR, US
- LinkedIn followers
- 500 followers
About Umer I. Cheema
Extensive experience in Accelerator Architectures, FPGAs, Neural Processing Units (NPUs), Micro-architecture/RTL Development, PPA Optimization, Floating-point Numerics, EDA Software Development, VLSI Physical Design and Embedded Systems-Skilled in Computer Architecture, Digital Circuit Design, FPGA Based Accelerators and Microprocessor-based system Design- PhD dissertation focused on Accelerator Architectures for memory and compute-intensive algorithms- Taught graduate and undergraduate level courses: Digital System Design, Microprocessor based System Design and Computer Architecture.
Experience
Deep Learning Hardware Engineer
Jan 2021 — Present · Portland, OR, US
Part of Advance Architecture Research Team working on next generation Deep Learning solutions from Intel.
Education
University of Engineering and Technology, Lahore
Bachelor of Science (B.Sc.), Electrical, Electronics and Communications Engineering
2004 — 2008
University of Illinois Chicago
Master of Science (MS), Electrical & Computer Engineering
2011 — 2014
Forman Christian College (A Chartered University)
F.Sc, Pre-Engineering
2002 — 2004
University of Illinois Chicago
Doctor of Philosophy (PhD), Electrical & Computer Engineering
2011 — 2016
Skills
- Digital Signal Processing
- Cadence
- Research
- Electrical Engineering
- Soc
- Tcl
- Teaching
- Windows
- Spice
- High Performance Computing
- Circuit Design
- Computer Architecture
- Latex
- Object Oriented Design
- Verilog
- Pspice
- Integrated Circuit Design
- Microprocessors
- Fpga
- Asic
- Microsoft Sql Server
- Digital Signal Processors
- Labview
- Microcontrollers
- Parallel Processing
- Algorithms
- C++
- I2c
- Vhdl
- Simulations
- Modelsim
- Signal Processing
- Simulink
- System Verilog
- Cadence Virtuoso
- Digital Circuit Design
- Vlsi
- C
- Programming
- Debugging
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