Kapil Usgaonkar
Design Engineering
- Role
- Sr Manager at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
General Business & ManagementView LinkedIn profile
About Kapil Usgaonkar
17 yrs of FPGA RTL coding, Synthesis, Simulation, Validation FPGA based board design…
Experience
Sr Manager
Feb 2022 — Present · Hyderabad, IN
Education
Goa University
BE
1997 — 2001
Skills
- Xilinx
- Systemverilog
- Pcb Design
- Programming Languages
- Rtl Coding
- Testing
- Static Timing Analysis
- Vhdl
- Simulations
- Debugging
- Fpga
- Asic
- Functional Verification
- Python
- Logic Synthesis
- Hardware
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