Ujas Patel
Power UPF engineer at Apple
- Role
- Power Upf Methodolody Engineer at Apple
- Location
- Dallas, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Ujas Patel
Dynamic engineer with Interest in Digital circuit design, Analog/Mixed signal & ASIC…
Experience
Power Upf Methodolody Engineer
Jul 2020 — Present · Austin, TX, US
Education
The University of Texas at Dallas
Master of Science (MS), Electrical Engineering
2014 — 2015
L.D. College of Engineering
Bachelor of Engineering (B.E.), Electronics and Communication Engineering
2009 — 2013
Skills
- Xilinx Ise
- Cadence
- Static Timing Analysis
- Synopsys Tools
- Mixed-Signal Ic Design
- C
- Microsoft Office
- Vlsi
- C++
- Cadence Virtuoso
- Verilog
- Pspice
- Logic Synthesis
- Circuit Design
- Analog Circuit Design
- Hspice
- Perl
- Integrated Circuit Design
- Cmos
- Spice
- Soc
- Physical Design
- Synopsys Primetime
- Xilinx
- Systemverilog
- Very-Large-Scale Integration (Vlsi)
- Semiconductors
- Computer Architecture
- Rtl Coding
- Rf
- Fpga
- Testing
- Asic
- Modelsim
- Place & Route
- Matlab
- Low-Power Design
- Awr Microwave Office
- Vhdl
- Simulations
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