Uditnarayan Mandal
Design Verification Engineer @ Bitsilica | Chip design and verification
- Role
- Design Verification Engineer at Wipro
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Uditnarayan Mandal
When I started learning Design Verification, I believed writing UVM code was the hardest…
Experience
Design Verification Engineer
Jun 2022 — Present · Bangalore Urban, IN
Experienced VLSI Project Engineer with a proven track record in creating comprehensive test cases and achieving 100% code coverage. Skilled in Verilog, Systemverilog, UVM, VHDL, Python, Perl, Cadence, Vivado, and other relevant technologies. Proficient in debugging via waveform analysis and log file interpretation. Actively seeking opportunities to apply my expertise in ASIC design, FPGA, and protocols including I2C, PCIe, AMBA, and USB. Eager to contribute to a dynamic team and drive collective success through collaborative problem-solving and innovative solutions.
Education
KiiT University
Bachelor of Technology - BTech
2015 — 2019
KiiT University
Master of Technology - MTech
2020 — 2022
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.