Udayasakthi S
Design Verification Engineer L1 | PCIe Controller & Subsystem - SoC
- Role
- Design Verification Engineer at Wipro
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Udayasakthi S
Hi, I\'m a DV Engineer with hands-on experience in PCIe IP & subsystem-level…
Experience
Design Verification Engineer
Jun 2024 — Present · Bengaluru, IN
Contracted to Intel• Verified PCIe Gen 3/4/5 at SoC level, ensuring protocol compliance and functional correctness.• Performed LTSSM validation, link training, and low-power feature checks (L1 sub-states, L0s).• Developed test sequences, ran regressions, and gained exposure to PCIe controller and subsystem-level.
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