Udaya Bhaskara Kovvuri
ASIC Power Engineer at Google
- Role
- Sr Asic Power Engineer at Google
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Udaya Bhaskara Kovvuri
Low power design with expertise across Architecture, RTL & layout power.Power Model development for SW optimization through instruction level power analysis.Hands on experience in Power Analysis, Optimization.RTL, Layout power estimation methodology development from scratch using Joules and Voltus.Solid understanding of PnR, clocking and standard cell design. Skilled in Verilog, System Verilog, Perl, Python & Tcl scripting languages.Tools: Voltus, PTPX, DC, ICC2, Genus, Innovus, Virtuoso, Joules.
Experience
Sr Asic Power Engineer
Sep 2025 — Present · Sunnyvale, CA, US
Education
University of South Florida
Master's degree, Electrical and Electronics Engineering
2014 — 2016
GITAM Deemed University
Bachelor’s Degree, Electrical, Electronics and Communications Engineering
2010 — 2014
Sri Chaitanya College of Education
Intermediate, Maths-Physics-Chemistry
2008 — 2010
Skills
- Microsoft Office
- Vlsi
- Leadership
- Rtl Design
- Matlab
- Verilog
- Python
- Perl
- Digital Electronics
- Cadence Virtuoso Layout Editor
- Cadence Encounter
- C
- Microprocessors
- Data Structures
- Asic
- Entrepreneurship
- Cadence Virtuoso
- Digital Circuit Design
- Xilinx Ise
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