Uday Palukuri
Senior Engineering Manager - Substrate Packaging Defect Metrology
- Role
- Senior Engineering Manager - Substrate Defect Metrology & Assembly Microcontamination at Intel
- Location
- Chandler, AZ, US
- LinkedIn followers
- 500 followers
About Uday Palukuri
16+ years of engineering experience in the semiconductor industry focused on Yield and Process Control in Front end process technology and Advanced Packaging.•Rich experience in developing advanced Yield tools and technologies in collaboration with OEMs.•Expertise in devising strategies/DOEs/Root cause Analysis for Yield enhancement and process development.•Strong understanding of Logic, Memory, and Advanced Packaging technologies.•Core competencies: People management, project management, technology development, technology transfer to HVMs, and CapEx optimization.•Diverse international work experience: Intel (USA), Micron (USA, Singapore), GlobalFoundries (Germany), TSMC (Taiwan), MXIC (Taiwan),SK Hynix (Korea), Infineon (Austria)+.
Experience
Senior Engineering Manager - Substrate Defect Metrology & Assembly Microcontamination
Apr 2026 — Present
Education
Indian Institute of Technology, Kharagpur
Master of Technology - MTech, Microelectronics and VLSI Design
2007 — 2009
Andhra University
Bachelor of Engineering - BE, Electronics and Communications Engineering
2003 — 2007
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