Uday Banala
DFT Intern @ STMicroelectronics | M.Tech VLSI Design (2024–2026) – VIT Vellore | Maven Silicon-Certified | ECE Graduate | Passionate about DFT & VLSI Design
- Role
- Dft Intern at STMicroelectronics
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Uday Banala
Results-driven DFT Engineer with hands-on industry experience at STMicroelectronics…
Experience
Dft Intern
Jul 2025 — Present · Bengaluru, IN
Working on Scan Insertion, ATPG and Simulation with a focus on generating test patterns for Stuck at and Transition faults by utilising Tetra max (Tmax) tool for pattern generation and test coverage analysis and Simulation of test patterns by utilising cadence V Manager and Xcelium Tools.
Education
Nalanda Vidhyanekethan High School
SSC
2017 — 2018
Vellore Institute of Technology
Master of Technology - MTech VLSI DESIGN
2024 — 2026
Parul University
Bachelor of Technology - BTech
2021 — 2024
TRR COLLEGE OF TECHNOLOGY
Polytechnic Diploma
2018 — 2021
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