Chetan Udawant

About Chetan Udawant

Hello,I\'m Chetan, an electrical engineering graduate student at the San Jose State University. I\'ve been working in verification domain from past 4 years. I\'m actively seeking Verification engineer position.I have solid understanding and strong background of digital logic design, computer architecture, and good hands on experience with SystemVerilog and UVM, hands on experience with coding, scripting. I\'ve played major role in the successful development of 6 complex Interface Verification IP (VIP) from scratch using SystemVerilog and UVM. Strong knowledge of AMBA APB, AHB, AHB-Lite, AXI4 and AXI4 Lite Interface Verification IP (VIP).SKILLS:• Programming Languages: SystemVerilog, SV Assertions, Verilog, C++, Assembly Language• Verification Methodology: Universal Verification Methodology (UVM)• Scripting languages: C shell, Perl, Python• Bus protocols: IMG BUS v1, v2 and v3, AMBA APB3 and APB4, AHB, AHB-Lite, AXI4 and AXI4-Lite• Operating systems: Linux and Windows• Tools: Cadence IES, IVB, Vmanager, Eplanner, Simvision, ncsim, DVT eclipse, Synopsys VCS, ncverilog, ModelSimPROFESSIONAL TRAINNINGS:• SystemVerilog language for verification (Cadence India.) • SystemVerilog Advanced Verification using UVM 1.1 (Cadence India.)• SystemVerilog Assertions (Cadence India.)Contact Info: E-mail ID: c••••••••@gmail.comContact No:+16•••••••41

Experience

1. Senior Design Verification Engineer

   NVIDIA

   Apr 2024 — Present · Santa Clara, CA, US

Education

• San José State University

  Master’s Degree, Electrical Engineering (VLSI)

  2015 — 2017

• Maharashtra Institute of Technology

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2010 — 2013

• Government Polytechnic College Nashik

  Diploma, Electrical, Electronics and Communications Engineering

  2007 — 2010

Skills

• Unix Shell Scripting
• Gtk Wave
• Vlsi
• Computer Architecture
• C
• Systemverilog
• Functional Verification
• Perl Scripting
• Amba Ahb
• Universal Verification Methodology (Uvm)
• Soc
• Perl
• Embedded Systems
• Verilog
• Axi4 and Axi4 Lite
• Synopsys Design Vision
• Matlab
• Amba
• Specman
• Uvm
• Nc-Verilog
• Cadence Incisiv
• Very-Large-Scale Integration (Vlsi)
• Synopsys Vcs
• Vhdl
• Shell Scripting
• C++
• Apb
• Synopsys Tools
• Debugging
• Linux
• Python