Udal Singh

ASIC Design Verification @ Meta | Ex-Intel | BETIC Lab | IIT Bombay

Role
Asic Design Verification Engineer at Meta
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

Experience

  1. Asic Design Verification Engineer

    Meta

    May 2025 — Present · Bengaluru, IN

Education

  • RGPV Bhopal (IGEC)

    Bachelor of Engineering - BE

    2010 — 2014

  • Indian Institute of Technology, Bombay

    Master of Technology - MTech

    2017 — 2019

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Udal Singh — Asic Design Verification Engineer at Meta in Bengaluru, KA, IN | Unifers