Tushar Gupta

About Tushar Gupta

Relevant Industry Work Experience: 8+ yrsSRAM/Register File architectures & advanced circuit implementations.Memory circuit design & characterization.Memory compiler development from specs to delivery. Bitcell analysis of 6T/8T design to characterize SNM, Leakage & Read/Write margins. Digital Logic Design -> RTL -> Synthesis -> STA -> CTS -> APR -> GDS in 7nm finfet PDK.ASIC implementation of MLP & Convolutional Neural Networks for CIFAR-10 & MNIST image classification.• Tools : Cdesigner, Virtuoso, Primetime, DC compiler, Encounter, Innovus, Synopsys IC Compiler, Modelsim.• Programming/Hardware Languages : Unix/Linux Shell, Python, Perl, Tcl, Verilog, System Verilog.• Circuit Simulators : HSpice, HSIM, CustomSim-XA, ICFB-spectre.

Experience

1. Sr Staff Engineer

   Samsung Electronics America

   Feb 2026 — Present · US

Education

• Kurukshetra University

  Bachelor of Technology (BTech), Electronics and Instrumention

  2005 — 2009

• Ira A. Fulton Schools of Engineering at Arizona State University

  Master of Science - MS, Electrical and Electronics Engineering

  2016 — 2018

• C - DAC, NOIDA

  PG Diploma, VLSI Design and Embedded Systems

  2010 — 2010

Skills

• C
• Microsoft Office
• High Level Synthesis
• Physical Design
• Drc/Lvs
• Cadence Spectre
• Perl
• C++
• Synplify Pro
• Research and Development (R&D)
• Circuit Design
• Application-Specific Integrated Circuits (Asic)
• Cmos
• Integrated Circuits (Ic)
• Static Timing Analysis
• Very-Large-Scale Integration (Vlsi)
• Rtl Verification
• Cadence Icfb
• Simulations
• Rtl Design
• Semiconductors
• Universal Verification Methodology (Uvm)
• Cadence Virtuoso
• Matlab
• Debugging
• Rtl to Gds
• Spice
• Hspice
• Cdesigner Synopsys
• Ovm
• Modelsim
• System Verilog
• Characterization
• Verilog
• Python
• Sta
• Analog Circuits
• Finfet