Tushar Dattatray Aher
Physical Design integration Engineer | Intel Corporation | Physical Design, Layout Verification & Full Chip Integration | 3DIC RDL Methodology | MIM Designing & RedHawk extraction | M.Sc Electronics 2021 | SPPU Pune
- Role
- Physical Design Integration Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Tushar Dattatray Aher
Tech nodes (Intel 3nm,Intel3 & Intel 18A), part of 6 Tape-ins, RDL routings MIMCAP generation 3DIC, Physical design integration, layout verification & sign off, of client and server SoC.
Experience
Physical Design Integration Engineer
Dec 2023 — Present · Bangalore Urban, IN
RDL planning, Routings (Top Metal/Back Metal), Physical integration, MIMCap planning and generation for client and server 3DIC SoC. MIM extraction on redhawk.>Full chip integration, layout verification and tape-in readiness.>Full chip floor planning, including lithography field optimization, architectural partitioning.
Education
Karmveer Kakasaheb Wagh Arts, science and Commerce College Pimpalgaon (Nashik) 422209
B.Sc , Electronic Science
2016 — 2019
Savitribai Phule Pune University
M.Sc, Electronic Science
2019
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