Tushar Arora
RTL Design Engineer @ Syllogism Technology | Verilog/SystemVerilog | PCIe Gen6 | AXI | FPGA | UVM | VLSI
- Role
- Design and Verification Engineer at Syllogism.In
- Location
- Sonipat, HR, IN
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Tushar Arora
RTL Design Engineer with hands-on experience in Verilog/SystemVerilog based RTL…
Experience
Design and Verification Engineer
Nov 2024 — Present
Education
Deenbandhu Chotu Ram University of Science & Technology
Bachelor of Technology - BTech
2020 — 2024
DAV Multipurpose public sonipat
Non Medical
2006 — 2020
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