Tim Fujiwara

About Tim Fujiwara

Over fifteen years of experience in physical design, backend and logic synthesis in hard macros and full chip SoC (ASIC).Three years of experience of product management and controlling Backend, STA and DFT teams.Experience in Hi- speed & Low power ARM core such as ARM7,ARM926,ARM946,VFP,ARM11,L2cache,CortexA9-1PE,2PE and 4PE hard-macroning,especially above 1GHz know-how.Knowledge of hard macro and full chip SoC small-area logic and physical synthesis using 130nm, 90nm, 45nm, 40nm and 28nm.B.E. in Electrical, Electronics and Computer Engineering with good command of English and Japanese.Holds 1 patent related to Clock tree synthesis.Hardware language: Verilog-HDL.Software language: csh, sed, awk, Perl, tcl, C.Backend Tools: IC Compiler, SOC Encounter (EDI), Magma Blast Fusion, Lavis, Calibre, VoltageStormSOC, QRC, StarRCXT, Celtic, Primetime-SI, PrimeTime-PX (Powercalc), Conformal Low Power, Conformal ECO, UPFSynthesis Tools: Design Compiler, Design Compiler-Topograph, RTL Compiler (Physical Layout Estimate Synthesis)FV Tools: Formality, Conformal LECSTA Tools: PrimeTime, TimeCraftDFT Tools: DFT Compiler, TetraMAXFE sim/viewer Tools: VCS, Incisive (NCVerilog), QuestaSim(Modelsim), Verdi, Spyglass

Experience

1. Engineering Manager

   Apple

   Nov 2018 — Present · San Francisco, CA, US

Education

• UCSC Silicon Valley Extension

  Embedded Systems & VLSI Engineering

  2014 — 2015

• Hiroshima University

  BSEE, Electric Engineering

  1997

Skills

• Sed
• Conformal
• Asic
• Edi
• Timing Closure
• Rtl Compiler
• Physical Synthesis
• Altera Quartus
• Design Compiler Topo
• Nc-Verilog
• Static Timing Analysis
• Primetime
• Calibre
• Tcl
• Arm Realview
• Awk
• Rtl Design
• Physical Design
• C
• Clock Tree Synthesis
• Starrcxt
• Perl
• Atpg
• Equivalence Checking
• Xilinx Vivado
• Verilog
• Compilers
• Csh
• Logic Synthesis
• Ic Compiler
• Low-Power Design
• Arm
• Vcs
• Ncsim
• Ncverilog
• Scan Insertion
• Modelsim
• Python
• Microprocessors
• Debussy