Trivid Singh
SOC Design Engineer at Intel | Ex-Samsung | Ex-Cadence
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Trivid Singh
8+ years of a diversified yet fructifying experience in the chip design. Problem solving roles catering to varied responsibilities within chip design Close to 8 tape-outs comprising of varying responsibilities within RTL2GDSII Flow Consistent believer in Automation for swifter TAT Fluent handshaking capabilities within cross-domain/cross-regional teams Desire to deep-dive into problems within semiconductor manufacturing and revenue forecasting for OEM considering the bigger perspective of overall business by expanding primary tech capabilities with the off-shore work in the investment arena identifying caveats in business model
Experience
Soc Design Engineer
Jul 2022 — Present · Bengaluru, IN
STA/SD Execution for Xeon/IFS IPs including intel caliber/STA/SD level implementation & Signoff\\\\nEnthusiastic about shifting to product management/developer relations role where I can extract the best within me.
Education
Birla Institute of Technology and Science, Pilani
Bachelor’s Degree, Electrical and Electronics Engineering
2009 — 2013
Birla Institute of Technology and Science, Pilani
Bachelor's degree, Electrical and Electronics Engineering, A-
2009 — 2014
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