Tritiya Erande
RTL Design Engineer@Intel
- Role
- Design Engineer Sr at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Tritiya Erande
I have 9 years of experience in RTL design on FPGA and ASIC platforms. And currently…
Experience
Design Engineer Sr
Jun 2022 — Present · Bengaluru, IN
Education
Swami Muktanand High School 400071
SSC( Maharashtra State Board), General Studies
2008 — 2009
A. C. Patil College of Engineering Navi Mumbai-410 210
Bachelor of Engineering (BE), Electronics Engineering
2011 — 2015
C-DAC ,Pune
PG-Diploma , vlsi design
2016 — 2017
S K Somaiya Vidyavihars College of Arts Science & Commerce Vidyavihar Mumbai 400 077
HSC (Maharashtra State Board), Science (PCMB)
2010 — 2011
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