Trishya Chirakala

About Trishya Chirakala

Results-driven Backend VLSI Physical Design Engineer with 3+ years of experience in block-level ASIC implementation from RTL to GDSII. Specialized in timing closure, congestion reduction, and signoff checks (DRC, LVS, IR) across multiple PVT corners. Proficient with industry-leading EDA tools including Cadence Innovus, Synopsys PrimeTime, and ICC2.Key Strengths- Timing Closure: Closed setup violations on 90%+ critical paths across 5 PVT corners using PrimeTime-driven ECO- Physical Design: Reduced routing congestion by 18% through optimized floor planning and macro placement- Signoff & Verification: Experienced in DRC, LVS, antenna, and IR drop analysis for tape-out readiness- Automation & Scripting: Skilled in TCL and Python for report parsing, metric extraction, and workflow automation- Collaboration: Effective cross-functional work with RTL, verification, and layout teams.Actively pursuing Physical Design, STA, or ASIC Backend roles in the US semiconductor industry. Open to onsite, hybrid, or remote opportunities.

Experience

1. Physical Design Engineer

   GlobalFoundries

   Aug 2025 — Present · MN, US

   Achieved timing-clean ASIC layouts by closing 90%+ setup violations across 5 PVT corners using PrimeTime ECO iterations- Reduced routing congestion by ~18% through enhanced floor planning and optimized macro placement- Improved post-CTS worst negative slack from ~320ps to within signoff limits using buffering, cell resizing, and Vt optimization- Defined comprehensive SDC constraints for clocks, IO delays, false paths, and multicycle paths- Mitigated late-stage signoff risks by early identification of DRC, LVS, antenna, and IR issues.

Education

• GITAM Deemed University

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2018 — 2022

• University of Minnesota

  Master of Science - MS, Electrical and Electronics Engineering