Travis Lemmer

About Travis Lemmer

Design implementation support for logical and physical synthesis. RTL, DFT, timing analysis and optimization, low power design, CTS, SI, and full flow design for productivity, repeatability, reentrancy, and metric results.Specialties: High Performance Core Synthesis, Low Power Design Techniques, Timing Closure Analysis, STA, Automated Metric Collection and Graphical Display of Flowstep-Sensitive Metrics

Experience

1. Physical Design Engineer

   AMD

   Aug 2025 — Present · Austin, TX, US

Education

• The University of Texas at Austin

  BSEE, Computer and Semiconductor Engineering

  2000 — 2003

Skills

• Lvs
• Ic
• Fpga
• Magma
• Signal Integrity
• Asic
• Drc
• Low Power Design
• Timing Closure
• Eda
• Static Timing Analysis
• Physical Design
• Rtl Design
• Soc
• Floorplanning
• Integrated Circuit Design
• Microprocessors
• Functional Verification
• Primetime
• Verilog
• Clock Tree Synthesis
• Mixed Signal
• Tcl
• Automation
• Physical Verification
• Vlsi
• Semiconductors
• Timing
• Low-Power Design
• Formal Verification
• Dft
• Processors
• Cmos