My T.

About My T.

Experience with Physical Verification and knowledgeable with Physical Implementation - Project management - Customer focus in CAD engineering in VLSI, IC, ASIC and SoC. Open to new opportunity to broaden my experience.Worked with many EDA Physical Verification tools from Cadence, Mentor Graphics and Synopsys for Physical Verification: Assura, PVL, IC Validator, Calibre DRC, LVS, ERC, DFM with broad-based success in developing and implementing full life-cycle projects. Knowledgeable in Physical Design Flow from Netlist to GDSII.Open to discuss career opportunity via my email m••••••@gmail.com or my phone 51••••••20. Can travel globally.Technical Skills:Physical Verification: DRC, LVS, ERC, PRE, DFM, Pattern Match, Design MethodologyPhysical Design: RTL2GDS, P&R, Synthesis, STA, LPE, Power Analysis, Area Analysis, Data flow AnalysisDesign Environment: Cadence Virtuoso, Allegro, Design Entry, Synopsys IC Workbench Plus, IC CompilerEDA Languages: Assura, PVL, IC Validator, Calibre, Hercules, Dracula, Simplex, ISS, Silicon Ensemble, VIDASLanguages: C, C++, Assembly, Python, Perl, Shell Scripts, Awk, Chameleon, HTML, CSSPlatform: Linux, Windows PC, Sun Sparc, Solaris OS, Unix, AIXSource Control: ClearCase, RCS, PVCSDocumentation: Microsoft Office, FrameMaker, Perforce, SharePoint

Experience

1. Cad

   pSemi, A Murata Company

   Aug 2018 — Present · San Diego, CA, US

   1) LVS in Cadence design environment with PVS2) LPE in Cadence design environment with PVS-Quantus, plus Parasitic extraction accuracy calibration 3) DRC supports Cadence design environment with PVS4) PDK strategic planning, execution, qualification and release management in Cliosoft environment5) Support for all PDKs (internal-built and OTS)6) PDK project management.

Education

• The University of Texas at Austin

  Bachelor of Science - BS, Computer and Electrical Engineering