Topomoy Dhar
Silicon Design Verification Engineer, Google | MTech , IIT Bombay, EE\'21 || GATE 2019- AIR 62
- Role
- Silicon Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Topomoy Dhar
ASIC/IP/Subsystem Design Verification Engineer in Google
Experience
Silicon Design Verification Engineer
Jul 2021 — Present · IN
Education
Sarada Vidya Mandir, Raiganj
CBSE(+2)
2009 — 2010
Jadavpur University
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2010 — 2014
Saint Xaviers School , Raiganj
ICSE
2007 — 2008
Indian Institute of Technology, Bombay
Master of Technology - MTech, Electrical, Electronics and Communications Engineering
2019
Skills
- Java
- Struts
- Html5
- Vbscript
- Javascript
- Css
- Selenium Grid
- Linux
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