Tom Lee

About Tom Lee

Over 20 years of experience in the area of timing analysis in both timing and frequency…

Experience

1. Infinera

   Jun 2018 — Present · Sunnyvale, US

   Responsible for the Selection/Validation/Qualification processes for Digital Semiconductor Devices.• Drive overall EOL/PCNs, 2nd Source Considerations/Alternate Part Recommendations with Internal Design and Supply Chain/Manuf. Teams.• Provide Technology Assessment support for Memories, Memory Modules, Frequency Sources and all Timing Devices.• Responsible for Digital Device Failure Analyze Processes by working with internal Teams. FA starts with Supplier RMA notification, Root Cause Analysis/Corrective Actions and 8D Report publication when applicable.• Responsible for Agile Data management on Digital Devices. Responsibilities include new Part Number Request (PNR) reviews, Supplier Datasheet reviews/updates, Char. Data Reviews. BOM risk assessment reviews, Manuf. Alerts generation, Char. Data Reviews, and Component MCO/ECO.• Support Agile related processes such as Component MCO/ECOs, BOM risk assessment reviews, Manuf. Alerts and Deviation Generations.

Education

• Santa Clara University Leavey School of Business

  MBA, Finance

  1982 — 1998

• California Polytechnic State University-San Luis Obispo

  BS, Electrical Engineering

  1972 — 1974

Skills

• Rf
• Testing
• Spice
• Static Timing Analysis
• Silicon
• Signal Integrity
• Hardware Architecture
• Semiconductors
• Serdes
• Pcb Design
• Cmos
• Mixed Signal
• Product Marketing
• Ic
• Engineering Management
• Analog Circuit Design
• Electronics
• Simulations
• Wireless
• Fpga
• Asic
• Pll
• Analog