Travis Kleeburg

About Travis Kleeburg

Travis joined Intel in 2011 working in the Hard IP group on multi-interface PHYs as an analog engineer. His job responsibilities include,micro architecture definition & exploration, mixed-signal validation, circuit design pathfinding, variation analysis, defining cad tool improvements, cad tool validation, design methodology, planning and execution of project deliverables. Over the past several years at Intel, Travis has developed expertise in the design of multi GHz data paths, high speed clock correction and distribution, reliability verification with Apache tools, mixed signal design and design for variation.Recently, Travis has moved to the LCPLL team and his focus their is on designing the LC cores and ensuring maximum scalability of the LC core architecture and on rigorous validation of the design. Prior to joining Intel, Travis received his Ph.D. with a specific focus area of low-power/low-voltage analog circuit design. He worked on a multitude of subsystems during this time including, delta sigma ADCs, clock data recovery circuits, optical communication front ends, RF transmitters, power supply boost converters, LC and RO based PLLs and photodiode structures. He was an associate instructor for 1 year, responsible for all aspects of an upper division engineering course which taught frequency domain analysis and digital circuit basics. As an associate instructor he was responsible for generating and delivering lectures, mentoring students, managing students expectations, course grading and managing the duties of four Teaching Assistants (TA). As a grad student he was a TA for 4 years and during that period he TA\'d 7 different courses. In the 3 years he spent at Davis as an undergrad, he took 17 upper division electrical engineering courses, almost 2x the required amount. He was an undergrad researcher for 3 ECE professors, worked for the lettuce genomics group as a python programmer and was a tutor for vector calculus at the UCD learning skills center.

Experience

1. Analog Design Manager

   Intel

   Feb 2017 — Present · Sacramento, CA, US

   Travis is currently responsible for the development of next generation high speed LC oscillators in support of wireline interfaces. Travis manages a team of talented designers, scopes and defines work for contingent workers, mentors junior engineers and is a key stakeholder for LC PLL development both executionally and techinically at Intel.

Education

• University of California, Davis

  Ph.D, Electrical Engineering

  2006 — 2012

• University of California, Davis

  M.S., Electrical Engineering

  2006 — 2010

• University of California, Davis

  B.S., Electrical Engineering

  2003 — 2006

• Ventura College

  A.A., Liberal Arts

  2000 — 2003

Skills

• Cadence
• Energy Harvesting
• Eclipse
• Simulink
• Spectre
• Rf
• Antenna Design
• Matlab
• C
• Agilent Ads
• University Teaching
• Trend Analysis
• Pcb Design
• Systemverilog
• Cadence Virtuoso
• Verilog-a
• High Speed Design
• Analog Circuit Design
• Antennas
• Microcontro
• Rf Design
• Verilog
• Photovoltaics
• Ansys
• Cmos
• Communication Systems
• Sensors
• Labview
• System Verilog
• Process Technology
• Optical Communications
• Python
• Latex
• Mixed Signal