Wentong Chen

About Wentong Chen

10+ years of ASIC front-end design experience in the roles of design manager, project manager, team lead and individual contributor. I led to tape out multiple video SoC successfully in the pass years and experienced all the phase of ASIC front-end design flow ranging from IP design, top level integration, verification, STA, CTS, DFT to SDK development and chip bring up.Specialties:* Verilog RTL coding * SOC architecture design/ chip top integration * Video/Image processing modules design * Verification method: UVM/OVM * DFT: SCAN/MBIST insertion, ATPG and test pattern bring up/debug.* Back-end interface: static timing analysis, clock tree generation.Knowledge: H.264, video/image processing, USB, MIPI-CSI, DDR, LCD, AHB, AXI,SD/MMC etc, Skills: Verilog,UVM, System Verilog, C, Perl, Shell Script, TCL

Experience

1. Principal Engineer

   Broadcom

   May 2017 — Present · San Jose, CA, US

   802.11AX Wifi MAC design. Wifi security system.

Education

• University of Science and Technology of China

  bachelor, Automation

  1994 — 1998

• University of Science and Technology of China

  MS, Electrical and Electronics Engineering

  1999 — 2002

Skills

• Verilog
• Dft
• Logic Synthesis
• C
• Debugging
• Rtl Design
• Usb
• Semiconductors
• H.264
• Arm
• Systemverilog
• Soc
• Vlsi
• Ic
• Static Timing Analysis
• Rc
• Perl
• Embedded Systems
• Eda
• Rtl Coding
• Fpga
• Asic
• Digital Signal Processors