Tim Low

About Tim Low

Tim was a platform architect for Intel with more than 25 years of experiences in mixed signal and analog VLSI design. Tim led number of designs and projects spanning across 7 generation of x86 CPUs Design & Development where he owned multiple patents in PLL architecture and IO adaptive equalization algorithms. He is an active member of the AMS community where he spent the past 15 years teaching analog behavioral modeling for rapid prototyping Top Down Architecture and mixed signal validation. He managed/trained mixed signal validation teams spanning across multi-geo that includes process and strategies, overseeing low level activities and facilitating growth in the team personal development. Specialties: Extensive knowledge in I/O circuit architecture (GTL, DDR, PCIe, UPI), Clocking design and architecture (PLL and clock distribution), and functional mixed-mode RTL modeling (Verilog-A/AMS, System Verilog, Verilog, Wreal).Once a technical lead for the Data Center Group, Tim is an expert in power delivery solution for Xeon server products that includes the architectural development of integrated voltage regulator (LDO, PWM, switch capacitor, DC-DC bulk converter, bandgap, etc)

Experience

1. Solutions Director

   Cadence

   Jul 2024 — Present

   Cadence Technical Lead for all aspects of the Rapidus Foundry engagement, drive comprehensive solutions for PDK technology enablement and ensure efficient project execution.

Education

• Oregon State University

  MS, Electrical Engineer

Skills

• Microprocessors
• Verilog
• Cadence Virtuoso
• Phase-Locked Loop (Pll)
• Mixed Signal
• Circuit Design
• Systemverilog
• Power Management
• Ddr
• Pcie
• Intel
• Cadence
• Ic
• Processors
• Cmos
• Rtl Design
• Verilog-a
• Asic
• Pll
• Analog
• Matlab
• Low-Power Design
• Computer Architecture
• Spectre
• Perl
• Dft
• C
• Debugging
• Vlsi
• Physical Design
• Analog Circuit Design
• Functional Verification
• Modelsim
• Soc