Thuy Tran

About Thuy Tran

10+ years Analog Mixed Signal Layout Designer would like to contribute the duties to the hiring fabless companies; to render the analog layout design services that to translate schematics to layout from the critical top blocks to finish the SOC, and support tape-out procedure; experienced to perform design fast for speeding up finishing the layout design projects; interacted with the project teams and communicated; layout designs experienced with TSMC7FF/TSMC5FF/TSMC3FF processes; will to adopt the new processes w/in quick time; used Cadence Virtuoso VXL; Calibre PDV; SkillCAD

Experience

1. Custom Analog Layout Designer

   Apple

   May 2021 — Present · Cupertino, CA, US

   Implementing custom Analog/mixed-signal circuits in state-of-the-art CMOS TSM3FF17LM. Performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption. Circuits for custom layout may include Analog, re-use IP, library\'s digital standard cells, resistors and capacitors, IO cells, ESD structures, High Speed Core/Converter, PLL, LDO, ADC, DAC, TX_RX. Performance Analog and high-power layout techniques used Cad Virtuoso ICADVM20.1-64b; Debugging the IC verification flow of DRC, LVS, XOR. used Calibre PDV.

Education

• Silicon Drafting Institute, San Jose, CA

  CMOS/RF Layout Design Techniques

• UCSC Silicon Valley Extension

  VLSI Design Engineering -

  2002 — 2003

• San José State University

  BSACM, Applied and Computational Mathematics

Skills

• Unix
• Manual Placement and Routing the Soc
• Eda
• Analog Layout Designs
• Layout Backgates && Double Guardrings
• Rfams Layout Designs
• Asic
• Very-Large-Scale Integration (Vlsi)
• Layout Shielding the Critical Nets
• Read Tcl/Tk Language
• Semiconductors
• Layout Prevent Latchup
• Analog Mixed Signal Layout Designs
• Pdk Property Editors
• Antenna_Drc Verification
• Xrc
• Cadence Virtuoso
• Vlsi
• Design Rule Checking (Drc)
• Read Skill Language
• Lvs
• Cadence
• Debugging
• Library Ip Layout Designs
• Calibre
• Application-Specific Integrated Circuits (Asic)
• Erc Verification
• Floorplanning the Layout
• Analog Circuit Design
• Ic Layout Designs
• Library Layout Development
• Generate Gdsii && Lef Files
• Cadence Virtuoso Layout Editor
• Testing
• Drc
• Implement Waived Errors on Layout
• Radio Frequency (Rf)
• Skillcad
• Layout Tsmc130/90/65/45/40/28 Processes
• Layout Matching/Isolation