Thomas Nguyen
RTL/ASIC/FPGA Design Engineer
- Role
- Asic Design Engineer Memory Subsystems at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Thomas Nguyen
I am a digital design engineer with experience in FPGA and ASIC implementation, focused on building high-performance, low-power, and low-latency systems. I have worked on a range of IP controllers designed for high-speed I/O protocols, such as PCIe Gen6, DDR4/DDR5, and 10/25-Gbps Ethernet. I have also contributed across the full front-end design flow, from microarchitecture and RTL development to timing closure, CDC and Lint checks, verification, and silicon bring-up. Along the way, I have also worked on high-frequency trading systems, machine learning accelerators, and data analytics platforms across both industry and academic environments.I enjoy solving complex technical challenges with best practices and thinking through systems with care, but I also place a high value on teamwork and open collaboration. I believe in learning from everyone, regardless of level or background, and sharing what I know in return. Mentorship has been a meaningful part of my work, and I do my best to support junior engineers whenever I can. To me, success is not just about delivering working hardware, it is about growing together as a team and building things that truly matter.
Experience
Asic Design Engineer Memory Subsystems
Jul 2025 — Present · Santa Clara, CA, US
Education
VNUHCM - University of Science
Bachelor of Science (B.Sc.), Electronics and Telecommunications
2006 — 2010
The University of Electro-Communications
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering
2014 — 2017
VNUHCM - University of Science
Master of Science (M.Sc.), Microelectronics
2011 — 2013
Skills
- Very-Large-Scale Integration (Vlsi)
- Programming Languages
- Python
- Data Analytics
- Field-Programmable Gate Arrays (Fpga)
- Application-Specific Integrated Circuits (Asic)
- Verilog
- C++
- Matlab
- Electrical Engineering
- C
- Computer Hardware
- C#
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