Thierry Besson
Principal Engineer at Zero Asic
- Role
- Principal Engineer at Zero Asic
- Location
- Boston, MA, US
- LinkedIn followers
- 500 followers
About Thierry Besson
35 years of expertise in EDA : Logic Synthesis, HDL Synthesis, Standard cells and FPGA back-end synthesis, Formal Verification, STA, P&R, Area/Timing and Power Optimizations, …, with strong background in C/C++ especially on UNIX/LINUX Platform, in Core Algorithmic and Data-Structures concepts, in Software Design Methodologies, strong commitment on project deliveries, several Management and Technical Leader experiences in an International environment.
Experience
Principal Engineer
May 2025 — Present
Education
INP Grenoble & UC Berkeley
Ph.D., Computer Science
1990 — 1996
University of California, Berkeley
Ph.D student at EECS department, UC Berkeley, CA, USA with Pr. R.K.Brayton
1991 — 1994
National School of Computer Science and Applied Mathematics of Grenoble
Ingénieur ENSIMAG, groupe ENSI (Ecoles Nationales Supérieures d'Ingénieurs), computer science (Software Engineering & Artificial Intelligence)
1987 — 1990
Skills
- Verilog
- Vhdl
- Systemverilog
- Rtl Design
- Logic Synthesis
- Soc
- Debugging
- Tcl
- Algorithms
- Physical Design
- Vlsi
- Asic
- Formal Verification
- Application-Specific Integrated Circuits (Asic)
- Functional Verification
- Static Timing Analysis
- Eda
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