Shamik Chakraborty
Design & Verification Engineer @ HCLTech | Design Engineer | RTL Development | ASIC & SoC Design
- Role
- Lead Engineer at HCLTech
- Location
- Kolkata, WB, IN
- LinkedIn followers
- 500 followers
About Shamik Chakraborty
RTL / ASIC Design Engineer with 3+ years of experience delivering low-power MCU SoC IPs from microarchitecture to silicon sign-off. Successfully contributed to 3 tape-outs, owning design and timing closure for multi-clock IP blocks operating at 32 MHz and 64 MHz. Strong expertise in Verilog/SystemVerilog RTL design, SDC constraint development, STA-driven timing closure, CDC/RDC sign-off, UPF-based power intent implementation, DFT scan insertion, and UVM-based verification.CORE COMPETENCIESRTL Design | Microarchitecture | Low-Power SoC Architecture | ASIC Design Flow | Synthesis | Timing Closure | Static Timing Analysis (STA)| SDC Constraints | CDC/RDC Analysis | Formal Verification | UPF | Multi-Clock Architecture | FSM Design | Pipelining | Area/Power/Performance Optimization | SoC Integration
Experience
Lead Engineer
Oct 2025 — Present · Kolkata, IN
Owned microarchitecture, RTL design, synthesis, and sign-off for multiple low-power SoC IPs including IOTOP, RAMSS, DAC Controller, ADC Controller, Power Optimization Module, and Timer subsystems.• Delivered 3 successful tape-outs for low-power MCU-based SoC platforms.• Created and validated SDC constraints for IP blocks operating at 32 MHz and 64 MHz, ensuring clean timing sign-off using STA.• Achieved timing closure across multi-clock domains through constraint refinement, pipeline optimization, and cross-domain synchronization strategies.• Performed CDC/RDC verification and formal checks, eliminating critical violations prior to tape-out.• Implemented UPF-based multi-power domain architecture, including isolation, retention, and power gating strategies.• Executed DFT scan mux insertion and scan validation, ensuring design-for-test compliance.• Contributed to UVM-based verification, developing testcases, running simulations, debugging waveform failures, and supporting regression closure.
Education
Maulana Abul Kalam Azad University of Technology, West Bengal formerly WBUT
Bachelor of Technology - BTech, Electrical Engineering
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