Rajat Chaudhary

About Rajat Chaudhary

10+ years of work experience in VLSI Physical Design.• Owned Complete Backend for Cortex A53 dual core CPU, STA ownership for Cortex A53 CPU (dual core) and DSU• Owned Multiple blocks across different tech nodes and foundries like TSMC 16ff+ to 7nm, Samsung - 14LPP to 5LPP• Responsible for complete Physical Design flow from Netlist to GDSII which includes Floor planning, Power planning, Placement, CTS, Routing, Crosstalk analysis, Parasitic Extraction, DRC, LVS, STA and ECO implementation.• Static Timing Analysis (STA) using Primetime for block timing closure.• Performed ECOs for timing closure, DRCs, Signal_em.• Approached a variety of timing problems with automated and custom manual fixes.• Developed useful scripts to tackle many DRCs upfront in the flow.• Have worked on High Frequency(~1.6GHz) 16FF+ Design• Handled blocks with 3-5 million+ gate complexity.• Part of 8+ SOCs Tapeout in different TechNodes.• Strong Team Player, passionate, highly motivated to work towards complex design problems• TCL scripting for design automation and flow improvement, intermediate Python knowledge.

Experience

1. Physical Design and Implementation Engineer

   Google

   Aug 2022 — Present · Bengaluru, IN

Education

• Birla Institute of Technology and Science, Pilani

  Bachelor of Engineering (BE Hons.), Electrical and Electronics Engineering

  2010 — 2014

Skills

• Microcontrollers
• Matlab
• Vhdl
• Ltspice
• Synopsys Ic Compiler
• Sql
• Linux
• Asic
• Primetime
• Engineering
• Windows
• Electrical Engineering
• Pl-Sql
• Java
• C
• Programming
• C++
• Verilog
• Pspice
• Electronics
• Eda
• Physical Design
• Synopsys Primetime
• Cadence Encounter