Thenappan Nachiappan
Dft Engineer @NVIDIA
Santa Clara, CA, US
EMAILS
t••••••••@nvidia.com
MOBILE NUMBERS
+14•••••••40
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WORK HISTORY
Jun 2016 — Present
Dft Engineer @NVIDIA
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Santa Clara, CA, US
EDUCATION
2001 — 2004
Government College of Technology, Coimbatore
Bachelor of Engineering (B.E.), Electrical and Electronics Engineering
1998 — 2001
PSG Polytechnic College
Diploma, Electrical and Electronics Engineering
SKILLS
Automatic Test Pattern Generation (Atpg)JtagVerilogDebuggingVery-Large-Scale Integration (Vlsi)FpgaAsicBistDftSocLogic DesignFunctional VerificationSystemverilogAtpgRtl DesignApplication-Specific Integrated Circuits (Asic)
ABOUT THENAPPAN NACHIAPPAN
Design for Test (DFT), ATPG, ASIC/FPGA functional verification, ASIC prototyping, RTL design and integration, FPGA implementation, Evaluation and integration IPs and hardware bring-up
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