Theja Agaram
Analog layout Engineer at Intel | MNNIT ALLAHABAD
- Role
- Layout Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Layout Engineer
Jun 2022 — Present · Bengaluru, IN
Worked on RX and TX Regulator (LDO Block) circuit layout in ongoing project on Intel lower technology node. I have good exposure in the 5nm and 7nm nodes.Good understanding of TX Data Path and Tx Driver Slices.Worked on Analog blocks like Op-Amp, Current mirrors, Level shifters, Latches and Band gap reference circuit.Running all physical verifications as DRC/LVS and DENALL (density).
Education
Madanapalli Institute of Technology & Science, Madanapalli
Bachelor of Technology - BTech
2017 — 2021
Motilal Nehru National Institute Of Technology
Master of Technology - MTech
2021 — 2023
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