Tharun Padmanabha Somashekar

Hardware Design & Validation Engineer | System Testing • Board Bring-Up • PCB Altium Designer • Digital Hardware • Verilog/System Verilog • Signal & Power Integrity | M.S. Computer Engineering | UNT | May 2025

Role
Hardware Design & Validation Engineer at Palo Alto Networks
Location
Santa Clara, CA, US
LinkedIn followers
500 followers

About Tharun Padmanabha Somashekar

I hold a Master’s degree in Computer Engineering from the University of North Texas and a Bachelor’s in Electronics and Communication Engineering. Through hands-on academic and industry experience, I’ve built a strong foundation in hardware design, validation, system reliability, and embedded development — with a focus on delivering production-ready solutions across regulated environments.At Tata Consultancy Services, I served as an Assistant System Engineer, where I conducted Worst Case Circuit Analysis (WCCA) on ARM Cortex-based platforms to ensure robustness under extreme conditions. I also managed component lifecycle and selection, performed SI/PI analysis using HyperLynx, and validated PCB designs in Altium Designer. These responsibilities honed my expertise in hardware validation, failure analysis (FMEA), and compliance engineering.At Siemens Healthineers, I supported the development of the Magnetic Track and Barcode Reader subsystem in Aptio® Automation, contributing to track validation and system responsiveness in clinical diagnostics. My work helped streamline lab workflows and improve turnaround time by integrating multi-track configurations.Throughout my academic journey, I led multiple hands-on projects in FPGA design (Vivado), PCB design (Altium Designer), and robotics using ROS2. I also developed embedded applications with LTspice, TINA-TI, and Python, further expanding my skill set into simulation, automation, and real-time systems.With OPT approved, I am actively seeking full-time opportunities where I can apply my skills in hardware design, embedded systems, and system-level validation. I am passionate about building reliable, innovative technologies and thrive in cross-functional engineering teams committed to excellence.S

Experience

  1. Hardware Design & Validation Engineer

    Palo Alto Networks

    Jan 2026 — Present · Santa Clara, CA, US

    Perform Electrical Design Validation Testing (EDVT) through board bring-up, power sequencing, clock/reset verification, interface validation, and PCB-level debugging to ensure reliable, production-ready hardware.

Education

  • University of North Texas

    Master's degree, Computer Engineering

  • Visvesvaraya Technological University (VTU)

    The Oxford College of Engineering -- Bachelor of Engineering - BE , Electrical, Electronics and Communications Engineering

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Tharun Padmanabha Somashekar — Hardware Design & Validation Engineer at Palo Alto Networks in Santa Clara, CA, US | Unifers