Tharun Keerthipati
ASIC Design Verification Engineer | PCIe Protocols (Gen6 & Below) | SystemVerilog | UVM | VLSI & Semiconductor
- Role
- Pcie Design Verification Engineer at Smartdv Technologies
- Location
- Tirupati Urban, AP, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Tharun Keerthipati
I am an ASIC Design Verification Engineer at SmartDV Technologies with experience in PCIe…
Experience
Pcie Design Verification Engineer
Aug 2024 — Present · Bangalore Urban, IN
Education
Sri Chaitanya College of Education
Intermediate
2018 — 2020
Sree Saraswati VidyaNiketan E.M High School
SSC
2017 — 2018
Jawaharlal Nehru Technological University Anantapur (JNTUA)
Bachelor of Technology - BTech
2020 — 2024
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