Tharun Deep

About Tharun Deep

7+ Years of experience in Static Timing Analysis and timing closure activities.• 3 Years of experience in writing timing constraints for top and block level.• Debugging for validation and quality checks for constraints involving clocks, exceptions and IO & fixing them.• Hands on experience in Block Level Timing closure, ECO methodology, Timing DRC fixes.• Completed 15+ Projects tapeout at in tech nodes 5nm, 7nm, 10nm, 28nm.• Hands on working experience in tools Tempus, Primetime, TimeVision, Star-RC, Tweaker. • Undergone 6 Months of Training in RV-VLSI Design Center in various aspects of VLSI Design.• Complete Understanding of ASIC Flow, and hands on experience in various stages of Physical Design.• Familiar with Linux and understanding scripting with PERL, TCL.

Experience

1. Engineer - 2

   Qualcomm

   Jun 2019 — Present · Bengaluru, IN

   Worked on multi voltage blocks and block level timing closure.• Understanding and providing fixes for timing drc.• Fixing the timing violations in the design with manual/tweaker ecos.• Worked on flows like LPPI and PG-Verilog for multivoltage domain timing closure.• Comparing the timing correlation from SOC to Block level and providing the fixes.• Proving the timing budgets to meet the interface timing.• Creating the setup for full chip tweaker for interface fixes.• Worked on validating the PG-Verilog vs LPPI timing correlation.• Worked on extraction flows and cleared issues to generate the spefs.• To publish the timing drc summary and to follow up with the block owner and track its closure.

Education

• Sai Vidya Institute of Technology

  Bachelor's degree, Electronics and Communications Engineering

  2009 — 2013

• Reva Institute For Engineering And Technology Studies

  Master's degree, VLSI and Embedded systems

  2013 — 2015

Skills

• Floorplanning
• Clock Tree Synthesis
• Rtl Coding
• Vhdl
• Linux
• Place & Route
• Fpga
• Asic
• C++
• C
• Physical Verification
• Rtl Design
• Integrated Circuit Design
• Microsoft Office
• Vlsi
• Cadence Virtuoso
• Matlab
• Analog Circuit Design
• Timing Closure
• Verilog
• Physical Design
• Routing