Thanneru Vanithavani
Design Verification Engineer
- Role
- Design Verification Engineer at BITSILICA
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Thanneru Vanithavani
Passionate and detail-oriented Design Verification Engineer specializing in SystemVerilog, UVM methodology.Adept at debugging complex designs, collaborating across teams, and optimizing verification flows for efficiency. Looking forward to opportunities where I can contribute my expertise to cutting-edge semiconductor projects.
Experience
Design Verification Engineer
Dec 2022 — Present · Hyderabad, IN
Education
Sreenidhi Institute of Science and Technology
Bachelor of Technology - BTech
2018 — 2022
Alphores junior college
INTERMEDIATE
2016 — 2019
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