Gl Krishna Reddy Tadi

About Gl Krishna Reddy Tadi

I am an experienced Verification Engineer with 7 years of expertise in both IP and SoC level verification. I have a deep understanding of SystemVerilog and UVM methodology, with a proven track record in developing and executing robust verification plans. My core experience includes working with a variety of protocols, including USB, SPI, AMBA (APB, AXI-lite), CAN, I3C, and I2C, ensuring high-quality deliverables in complex projects.I specialize in building efficient testbenches, performing thorough coverage analysis, and debugging complex verification challenges. I am well-versed in industry-leading EDA tools like Cadence Xcelium and Synopsys VCS, allowing me to contribute effectively to verification environments.Key skills include:Verification Methodologies: UVM, OVMProgramming Languages: Verilog, SystemVerilog, CProtocols: USB, SPI, AMBA (APB, AXI-lite), CAN, I3C, I2CTools & Environments: Cadence Xcelium, Synopsys VCSWith a passion for problem-solving and a focus on high-quality verification, I continuously strive to optimize verification processes and ensure reliable product delivery.

Experience

1. Senior Silicon Design Engineer

   AMD

   Apr 2024 — Present · Hyderabad, IN

   Project12:(Aug 2025 - present)Working on axi-xspi- Developed uvm test bench from scratch using xam uvc to verify hyperbus functionality- Integrated Ral env using xam uvc in testbench- Made Verification plan and testplan for hyperbus functionality - developing test cases and sequences to verify hyperbus functionality Project11:(May 2025 - July 2025)Worked on axi-gpio for functional safety - Developed uvm test cases to check safety measure of IP- Modififed existing testbench and updated to support VCS flow- worked on VCS merged coverage reports on VIPER(viper is a framework which take care of Regression and generate reports)- Made testplan, verification plan, coverage plan and other functional safety verification documentsProject 10:(March 2025 - April 2025)Worked on CANFD- understand the existing IP working- worked with Designers to bring up Design Architecture for Multichannel CANFD(existing IP is single channel)Project9:(Dec 2024 - Feb 2025)Worked on axi-gpio- Developed uvm testbench bench from scratch which is for a legacy IP- integrated Ral agent and xam uvc in testbench- written cover groups for axi gpio- Made testplan, verification plan, coverage plan and other verification documentsproject8:(May 2024 - Nov 2024)worked on I3C(Target)- Developed Testbench from scratch- Verified Registers using RAL- Verified I3c Target, which supports for only SDR mode- Implemented checkers for check Data- Verified interrupts- Verified all controller response codes- Verified PEC feature- Verified IBI functionality(with and with out payloads)- Verified Hot Join functionality- verified secondary controller functionality- implemented error injection test-cases(start, stop,parity bit,T bit, pec byte corruption)

Education

• Vellore Institute of Technology

  Master of Technology - MTech, Power Electronics and Drives

• Aditya University

  Bachelor of Technology - BTech, Electrical and Electronics Engineering