Tevien Toliver

Experience

1. Pre-silicon Formal Verification Engineer

   Samsung Semiconductor

   May 2023 — Present · Austin, TX, US

   Spearheaded sequence-based verification (SEQ) strategies for GPU architecture, prioritizing validation of power-critical features like clock gating, memory subsystems, and low-power control logic.• Design and executed SEQ test plans to verify GPU specific power management units and clock domain behaviors, ensuring seamless integration of energy-saving features• Collaborated with architecture teams to align FPV and SEQ coverage goals for new GPU features, streamlining verification of power and performance requirements.• Applied formal verification tools (JasperGold, VC Formal) to validate various features in GPU power management (dynamic clock gating) and functional logic (memory arbitration, control units) ensuring robust design quality.

Education

• Virginia State University

  Bachelor of Science - BS, Computer Engineering

  2014 — 2018