Tej Kola

About Tej Kola

Hello! I\'m a passionate DV (Design Verification) Engineer with extensive experience in debugging and validating digital designs. My expertise lies in hardware description languages like Verilog and SystemVerilog, as well as using methodologies like UVM (Universal Verification Methodology) to ensure the quality and functionality of complex designs.Throughout my career, I\'ve had the opportunity to work on diverse projects, including USB and CNV Specman projects for Intel. These experiences have equipped me with a deep understanding of the verification process and the ability to tackle challenging verification tasks effectively.In addition to my language and methodology skills, I\'m well-versed in various verification tools, with a strong proficiency in using Verdi for debugging and analysis.I thrive in collaborative environments and enjoy working with cross-functional teams to deliver high-quality products. As a problem solver and detail-oriented professional, I take pride in delivering robust and reliable verification solutions to ensure the success of each project I\'m involved in.

Experience

1. Vlsi Engineer (Ideas -er & d)

   Wipro

   Jul 2021 — Present · Bengaluru, IN

Education

• Bansal Public School

  Intermediate, Science

  2015 — 2017

• Sri Chaitanya Techno School - Visakhapatnam

  Matriculation

  2013 — 2015

• National Institute of Technology Rourkela

  Bachelor of Technology - BTech

  2017 — 2021