Tejaswi Maradani
Seeking Full Time | ASIC | RTL (Verilog, SV, UVM, FSM, SVA) | STA | Code & Functional Coverage | PMICs, DC-DC Converters | PSpice Modeling & Validation
- Role
- Senior Engineer at HCLTech
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Tejaswi Maradani
I’m a Design Engineer with over 4 years of hands-on experience in the semiconductor…
Experience
Senior Engineer
Jul 2023 — Present · Hubli, IN
Education
Sri Chaitanya College of Education
Intermediate (Class 11 & 12)
2015 — 2017
Vellore Institute of Technology
Bachelor of Technology
2017 — 2021
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.