Tejas Ramesh

About Tejas Ramesh

Passionate and Innovative Electrical Engineering Graduate Student with good technical as well as practical knowledge.•Domains of expertise: Digital Systems and Circuit Design, VLSI Design(Proficient in APR Flow).•Programming and Scripting Languages: C, C++, Verilog, System Verilog, Perl, TCL.•EDA Tools: Cadence Virtuoso,RTL Compiler, Encounter, Innovus, Synopsys IC Compiler, Design Compiler, Primetime, VCS, HSPICE, Calibre, Hercules DRC, LVS and PEX.•Operating Systems: Windows, Mac OS, Linux.•Currently working on 7nm PDK, Experience in 28nm and 32nm PDK designs.Coursework:SPRING \'16: Digital Systems and Circuit Design, Analog Integrated Circuits, Low power bio-electronicsFALL 2016: VLSI Design, System-Level Design for Multicore ArchitecturesSPRING \' 17: Hardware Acceleration and FPGA Computing Constructionist Approach to Microprocessor Design Computer Architecture II

Experience

1. Physical Design Engineer

   Apple

   May 2018 — Present · Austin, TX, US

Education

• Jawaharlal Nehru Technological University

  Bachelor’s Degree, Electronics and Communications Engineering

  2010 — 2014

• Arizona State University

  Master’s Degree, Electrical and Electronics Engineering

  2016 — 2017

Skills

• Tcl
• C++
• Rtl Design
• Manufacturing
• Microsoft Excel
• Computer Architecture
• Field-Programmable Gate Arrays (Fpga)
• Microsoft Powerpoint
• Sva(Sv Assertions)
• Product Development
• Perl
• Embedded Systems
• Universal Verification Methodology (Uvm)
• Vhdl
• Cross-Functional Team Leadership
• Analog Circuit Design
• Cadence Virtuoso
• Digital Circuit Design
• Python
• Hspice
• Verilog
• Matlab
• Questasim
• C
• Programming
• Very-Large-Scale Integration (Vlsi)
• Systemverilog
• Synopsys Primetime
• Linux
• Cadence Encounter
• Microsoft Office
• Cadence Rc
• Object-Oriented Programming (Oop)
• Synopsys Vcs