Tejal J.
Post Silicon Validation Engineer
- Role
- Memory Validation Engineer at AMD
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Tejal J.
Working as a System validation performing functional validation in commercial and synthetic validation environment in pre and post silicon validation phase for Client and SoCs for IPs such as USB, HD-Audio.
Experience
Memory Validation Engineer
May 2024 — Present · Santa Clara, CA, US
Education
Portland State University
Masters in Science, Electrical and Computer Engineering
Savitribai Phule Pune University
Bachelors in engineering, Electronocs and Telecommunication
Skills
- Rtl Design
- Ddr4
- Cmos
- Vhdl
- Verilog
- Shell Scripting
- Logic Analyzer
- Assembly Language
- Testing
- Matlab
- Semiconductors
- Xilinx Ise
- Usb
- Hd Audio
- C
- Vlsi
- Dynamic Random-Access Memory (Dram)
- Python
- Fpga Prototyping
- Perl Automation
- C++
- Debugging
- Computer Architecture
- Fpga
- Asic
- Linux
- Modelsim
- Field-Programmable Gate Arrays (Fpga)
- Perl
- Computer System Validation
- Unix
- Cadence Virtuoso
- Digital Circuit Design
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.