Tarun Patil
Sr. DFT Engineer at NVIDIA
- Role
- Senior Dft Engineer at NVIDIA
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Tarun Patil
Experienced ASIC Engineer with expertise in Design-for-test (DFT)/ Scan/ ATPG. Master\'s Degree focused in Computer Engineering from Virginia Tech. Skilled in Digital-design/ Verification, Design Automation and Design-for-test.
Experience
Senior Dft Engineer
Jul 2020 — Present · Bengaluru, IN
Education
RV College Of Engineering
Bachelor's Degree, Electrical, Electronics and Communications Engineering
2010 — 2014
Virginia Tech
Master's Degree, Computer Engineering
2014 — 2016
Skills
- Verilog
- Rtl Design
- Eda
- Ovm/ Uvm
- Synopsys Vcs
- Fpga Prototyping
- C++
- Java
- Embedded C
- Opencv
- Vlsi Cad
- Matlab
- Digital Image Processing
- Quantitative Analytics
- Rtl Verification
- Unix
- Programming
- Test Engineering
- Vlsi
- Computer Vision
- Vhdl
- Atpg
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.