Taruni Sanjay

About Taruni Sanjay

As an enthusiastic and detailed oriented engineer, I have specialized in high-speed digital design and verification with a focus on Ethernet standards 802.3) for the last 1.5 years. I have extensive experience in designing and verifying Ethernet MAC, PCS, and PHY layers, as well as implementing high-performance, low-latency systems. I am passionate about creating robust, high-performance solutions. With a Master’s degree in Electrical and Computer Engineering from the University of Maryland, College Park, I’ve developed a solid foundation in both design and verification methodologies.My expertise lies in digital design, verification, and simulation, with a strong proficiency in SystemVerilog, UVM, and Verilog HDL. I have hands-on experience working with industry-standard tools like QuestaSim, Synopsys DVE, Cadence Simvision, and Xilinx Vivado, as well as a range of programming languages including C/C++, Python, and Bash. I thrive in collaborative environments where innovation and efficiency are key. I am actively seeking new opportunities in ASIC/FPGA/SoC Design and Verification engineering, where I can leverage my skills to contribute to impactful projects and continue to grow as an engineer.

Experience

1. Fpga Design Engineer

   Pixels on Target LLC

   Jan 2025 — Present · Sunrise, FL, US

Education

• Vellore Institute of Technology

  Bachelor's degree, Electrical, Electronics and Communications Engineering

• University of Maryland

  Master of Engineering - MEng, Electrical and computer engineering