Tarun Kumar Adari

About Tarun Kumar Adari

Worked on Intel-3nm Finfet, TSMC - 3nm Finfet,5nm Finfet & 180nm CMOS and GF-22nm FDSOI & 14nm Finfet technologies.• Working on 80GTS-PMA3 & 40GTS-NRZ dual lane USB4.0 (Supports eDP,HDMI2.1,DP2.0) transmitter clock path(Generation of 2UI and 4UI differential clocks, 4UI pulses for different data rates form single ended pll clock) & data path ( Conversion of 40bit of 40UI data to 1bit of 1UI data with pre and post cursor data for driver FFE) and receiver clock path(Generation of I-Q differential clocks using PI, division clocks and duty cycle control from 5-phase single ended DCO clock) on INTEL 3nm Finfet technology.• Worked on 112GTS/116GTS- PAM4, 5-tap DAC based ethernet transmitter clock path(Generation of 4UI differential I-Q clocks & 1UI pulses from pll differential clock with duty cycle control & edge control) and data path(conversion of 9*64bit of 64UI data to 9*4bit of 4UI data). Understand the driver architecture to work on clock calibration algorithms on TSMC 5nm Finfet technology.• Worked on 224GTS - PAM4 ethernet transmitter clock path ( Generation of I-Q differential clocks & 1UI pulses from pll clock with duty cycle control & edge control and clock distribution network for 4lanes with inductors) on TSMC-3nm Finfet technology.• Worked on Proximity sensor and ambient light sensor using transimpedance amplifier (light to voltage converter) and light to frequency converters on TSMC 180nm CMOS technology. • Worked on 4GHz low jitter(4ps) type-II PLL and its sub blocks like PFD, CP, VCO, Dividers on GF22nm FDSOI technology.• Worked on 0.83V - 40mA(-25dB peak psr) NMOS LDO using cascade LDO\'s technique and 1.2V - 10mA PMOS LDO on GF22nm FDSOI technology.• Experience in design of 0.83V BGR, 1.12V BGR and 0.5V CMOS BGR, constant - gm bias, V2I and voltage reference generators on different technologies.• Design experience in building blocks of IP like POR, level shifter, opamp\'s, temperature monitors, power sniffer, schmitt triggers, flops, custom standard cells and dividers. etc.• Knowledge on basic layout techniques like floorplan, routing, matching, shielding, latch up, antenna effects, WPE….etc.• Knowledge of design for reliability i.e. EM, IR, SOA(EOS) and aging analysis.• Experience in generation of libs using cadence LIBERATE tool and synopsys siliconsmart.• Familiar with customer release files like lef, gds, cdl, datasheet, user guide, RNKPS, Verilog and libs.• Familiar with QA analysis like file existence, cross checks, Quality checks and compilation checks for customer releases.

Experience

1. R & d Analog Design

   高通

   Feb 2025 — Present · Bengaluru, IN

Education

• Andhra polytechnic, Kakinada

  Diploma, Electronics and Communications Engineering

  2010 — 2013

• Mahatma Gandhi Institute of Technology

  Bachelor of Technology - BTech, Electronics and communication

  2013 — 2016

• PRG boys high school, Kakinada

  High school

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Microelectronics

  2018 — 2020