Tarun J Kurian

Experience

1. Pde, Engineering Manager

   Intel

   Jan 2016 — Present

   Integrate and verify full chip & IP test methods, on-chip DFT/DFM solutions for complex multi-core Server, client and SoC products. • Develop and debug programs and test program flows to convert design validation vectors and drive ATE tester platform programming during silicon bring up phase to release in HVM environment. • Deploy Test Program collaterals and readiness for NPI’s, ensuring reliability, and performance of processors from the development stage into HVM. • Drive test optimizations to achieve higher coverage, reduce test cost, hardware capacity, improve yield efficiency, and optimizations to accelerate manufacturing stability. • Statistical analysis of parameters tested and defining optimal test pass/fail criteria on die level and ensure data integrity. • Analyze and evaluate component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. • Collaborate with global cross-functional teams including software, design, manufacturing, and engineering teams to drive effective test content capability throughout the entire product life cycle. • Validate, modify, and re-design circuits to guarantee component margin to specification, evaluate the robustness of new product designs to variations in the FAB process. • Efficiency and convergence via evaluation and development of sort/class test methodologies, standardization, and proliferation of best practices within and across product segments.