Tarun Goyal

About Tarun Goyal

Highly specialized and result-oriented Principal DFT Engineer with 10+ successful tape outs in 9 years of experience in defining, implementing, and validating complex Design-for-Test (DFT) architectures for high-performance ASICs across advanced process nodes. Expertise spans the full DFT flow, including DFT IP in RTL, Scan Insertion, high-coverage ATPG, pattern verification, Emulation and post silicon support. Proven ability to optimize test methodologies, reduce manufacturing test costs, and collaborate cross-functionally to achieve high-quality silicon deliveryo 5nm Auto Processor SoC test challenges and Defect oriented test(DoT)- Day1 Silicon Bring-upo Hands-on experience on SCAN, ATPG, JTAG, SSN & DFT IP integration (RTL or netlist).o DFT specifications & architecture development based on test quality (DPPM & Yield) & test cost (time). o Cross-domain knowledge CLP/UPF, STA, RTL, & System Verilog. o Silicon Bring-up for 5nm/16nm/28nm/40nm, tester log analyzing & debug experience. o Logic BIST, HTOL/Burn-in Tests, PG Simulations.o AI and Automation: Coverage Predictor and Ability to write scripts in Perl, Shell, TCL, etc.o 10 Tapeouts, top-notch work ethics, and professionalism.Academic Experience o Strong engineering professional. o M.Tech, Embedded Systems (VLSI) from Malaviya National Insitute of Technology Jaipur. o Crypto Algo implementation in C or MATLAB.o Hardware implementation (RTL to GDS-II) for Asymmetric Crypto Algorithms.

Experience

1. Principal Engineer

   NXP Semiconductors

   Apr 2024 — Present · Bengaluru, IN

   Pursuing 5 patents in Scan, DFT-Debug, SSN, and ATPG- Leading DFT for industry’s first 5nm Auto Processor SoC- Develop Scalable ATPG flows, SSN methodologies, and deployed on 4 SoC’s - Various Coverage techniques and enhancement for SA Coverage >99.5% & TD >97%- FTRV and Silicon Bring-up: First Wafer touch bring-up for 5 SoCs - Working on Zero defect Test and high-speed synchronous interface testing- Contributing in various methodology like Kaleidoscop, ZIOX, Veloce - Drove Test Cost Reduction and Pattern Optimization:~40% test pattern volume & time

Education

• University College of Engineering kota

  B.Tech, Electronics and Communication

  2010 — 2014

• Malaviya National Insitute of Technology Jaipur

  M.Tech, Embedded Systems

  2014 — 2016