Tarun Arora

About Tarun Arora

AMD Physical Verification SOCSoC Level DRC, LVS, ANT, PERC, DFM, ESDTSMC 6nmST MicroelectronicsPhysical Design Verification Expert in TSMC 7nm and 5nm ADAS SoC.SoC level DRC,LVS,PERC,DFM,ANTENNATapeout experience of TSMC7nm ADAS SoCMethodologies development for TSMC 5nm ADAS SoCCustom Routing of Analog IPs with PERC GuidelinesExpert in handling Mentor Calibre and Synopsys ICV Tools for Physical VerificationGood understanding of Cadence Innovus toolTCL scriptingClosely worked with SoC PNR engineer to streamline Physical Verification requirements.Worked with block owners to resolve and streamline DRC, Integration and other issues at SoCIntelPhysical design implementation for 14nm SoCSynthesis, PNR, ICC2Synopsys Full custom SRAM memory layout design for 3 years at different FINFET technology nodes 5nm/7nm/12nm/14nm. Expertise in designing layout for several blocks of SRAM memory compilers and physical verifications DRC, LVS, DFM, EM/IR.Great understanding of designing critical block requiring concepts like Matching, Shielding. Have gone through several release phases includes LEF release, test chip gds release, full compiler release. Good experience in checking for feasibility and implementing of ECO in design. Followed by QA for compiler release. Knowledge of challenges in recent technology nodes and it\'s impact on layout design. Good understanding for device fabrication and device physics. Experience of handling maskless photolithography for 2+ years.

Experience

1. Mts Server Soc Pdv

   AMD

   Jun 2024 — Present · Hyderabad, IN

Education

• Accurate Institute Of Managment And Technology

  Bachelor's Degree, Electronics and Communications Engineering

  2008 — 2012

Skills

• C
• Molecular Memories
• Lithography
• Emir
• Microprocessors
• Microcontrollers
• Cmos
• Vlsi Technology
• Characterization
• Vhdl
• Simulations
• Vlsi
• Wafer Cleaning
• Keithley Cv Iv Measurements
• Afm(Atomic Force Microscopy)
• Nanometric Devices
• Verilog
• Semiconductor Process Technology
• Soft Lithography
• Layout Versus Schematic (Lvs)
• Spin Coating
• Adiabatic Logic Design
• Graphene
• Thermal Evaporation
• Maskless Lithography
• Very-Large-Scale Integration (Vlsi)
• Design Rule Checking (Drc)
• C++
• Mos Device Simulation
• Soc
• Mos Layout Design
• Matlab
• Semiconductor Fabrication
• Asic
• Digital and Analog Cmos Design
• Semiconductors
• Flash Memories
• Mosfet Device Physics
• Embedded Systems